1. Field of the Invention
The present invention relates to an SRAM (Static Random Access Memory) cell that performs read and write operations through a single bit line.
2. Description of the Related Art
In the present application, a nodal point between circuits in an electric circuit network will be referred to as a node. Naturally, one node may fulfill two different roles. In other words, assumed that a partial circuit network having a specified function in a single circuit network is referred to as a partial circuit, when an electric signal is output from the partial circuit to a node (output signal node), this node may be recognized as a node into which an electric signal is input (input signal node) if seen from a different partial circuit connected to the node. In addition, a wiring for supplying current to a circuit is referred to as a power supply line, while a wiring to which the current having passed through the circuit is fed back from the power supply line is referred to as a power feedback line. Moreover, a terminal is used herein to refer to an electrode provided to establish external electric connections for circuit elements, such as transistors, resistors, and capacitors, used in the circuit. Electrically, the terminal may double as the node.
An electric circuit network is referred to as a logic device, which electrically performs the logical manipulation by corresponding logic values to two different values representative of the electric signals, e.g. high and low levels of signal amplitude. The electric signal in that case is referred to as a logic signal, having an either logic value 1 or 0, corresponding to the high level (H) or low level (L), respectively. The logic signal may be referred to simply as data. The electric signal for controlling electric operation of the electric circuit or an active device used therein is referred to as a control signal. The logic signal may double as the control signal. The wiring concerned with the control signal is referred to as a control signal line, while the wiring concerned with the logic signal is referred as a data line.
A transistor is one of embodied examples of an electric switch which has at least one control signal input terminal and at least two signal output terminals and which controls conducted/non-conducted state between two output terminals by means of the control signal. Such a transistor includes generally an insulated gate field effect transistor (MOST), a bipolar transistor (BET), and the like. For the MOST, a gate thereof is used as the control signal input terminal, while a drain and a source thereof are used as the two signal output terminals. For the BPT, a base thereof is used as the control signal input terminal, while a collector and an emitter thereof are used as the two signal output terminals.
In addition, an inverter is an electric circuit having signal input and output terminals, and is also a logic device capable of electrically performing the logical manipulation, in which the signal output terminal outputs an inverse logic signal of a logic signal applied to the signal input terminal. Of course, it operates while connected to the power supply line and the power feedback line.
The present invention will be described hereinafter exemplifying the case where the MOST is used as the transistor. An example of an SRAM cell using the MOST is a dual bit line SRAM cell 10 shown in FIG. 1. The term “bit line” herein refers to the data line, or a wiring through which input/output (writing/reading) of logic signals (data) of memory contents into/from the SRAM cell is performed. The term “dual” represents that there are two bit lines and that the logic signals passing therethrough simultaneously are inverse from each other. The bit lines include a write-only bit line, a read-only bit line, and a bit line that performs the both.
In FIG. 1, an inverter 12 is configured by a P-type MOST (PMOST) 20 and an N-type MOST (NMOST) 22 having each drain connected to an output signal node Q1, each gate electrode to an input signal node I1, a source of the PMOST 20 to a power supply line VDDL at a node VD1, and a source of the NMOST 22 to a power feedback line VSSL at a node VS1. Similarly, an inverter 14 is configured by a PMOST 24 and an NMOST 26 having each drain connected to an output signal node Q2, each gate to an input signal node 12, a source of the PMOST 24 to a power supply line VDDL at a node VD2, and a source of the NMOST 26 to a power feedback line VSSL at a node VS2. An inverter configured by the PMOST and the NMOST as described above is referred to as a CMOS inverter.
Then, the output signal node Q1 of the inverter 12 is connected to the input signal node I2 of the inverter 14, while the output signal node Q2 of the inverter 14 is connected to the input signal node I1 of the inverter 12, so that a positive feedback circuit (or a latch circuit) is configured. In addition, the output signal node Q2 of the inverter 14 is connected to a source (or a drain) of an NMOST 16 serving as an access transistor (a control transistor used for both read operation and write operation), the drain (or the source) of the NMOST 16 is connected to a bit line BL at a node D1, the output signal node Q1 of the inverter 12 is connected to a source (or a drain) of an NMOST 18 serving as another access transistor, the drain (or the source) of the NMOST 18 is connected to a bit line BLB at a node D2, and gates of the NMOSTs 16 and 18 are connected to word lines WL at nodes P1 and P2, respectively. In this way, a single SRAM cell is configured. The bit lines BL and BLB are complementary to each other, that is, potentials thereof when seen as the logic signals are inverse from each other. Logic signal levels of the output signal nodes Q1 and Q2 are also complementary to each other at a steady state (when one is at the high level H, the other is at the low level L). For example, the memory contents are determined such that, when the output signal node Q1 of the inverter 12 is at the low level and the output signal node Q2 of the inverter 14 is at the high level, a logic 1 is stored, or in the inverse status, a logic 0 is stored, and the like. The NMOSTs 16 and 18 are used as a read control transistor for reading the memory contents of the SRAM cell out to the bit lines BL and BLB, or as a write control transistor for writing the logic signals of the bit lines BL and BLB into the SRAM cell. Moreover, the logic signal level of the SRAM cell may be inconsistent with the logic signal level of a logic circuit external to the memory device using the same.
An SRAM device configured by an array of the SRAM cells is required to be capable of performing high-speed operation and having large storage capacity. Therefore, it is desired to reduce the area of the SRAM cells, or miniaturize the size of each transistor as much as practically possible. However, it is impossible to minimize all the transistors due to the requirements to prevent malfunctioning of the memory contents in the SRAM cell to be inverted when read out, or to ensure the memory contents to be written correctly. Thus, the channel lengths of the NMOSTs 22 and 26 of the inverter are made to be substantially minimum (the channel widths are usually made to be wider than the minimum size in consideration of the area and the operation speed), and the access transistors 16 and 18 are made to have less current drive capacity (e.g. the channel widths are narrowed, the channel lengths are extended, or both) while having more current drive capacity than those of the PMOST 20 of the inverter 12 and the PMOST 24 of the inverter 14 (e.g. the channel lengths of the PMOSTs 20 and 24 are extended than those of the access transistors 16 and 18, the channel widths thereof are narrowed than those, or both). Here, in consideration of the constraint that the channel width cannot be narrowed less than the feasible minimum size, the channel width of each transistor must be set to be wider than the minimum size. This results in the increase in the area of the SRAM cell and in the stray capacitance, leading to the decrease in the operation speed of the SRAM cell.
Patent Document 1 listed below discloses the circuit shown in FIG. 2 as a conventional SRAM cell without the size constraints imposed on each transistor configuring the SRAM cell described above.
In FIG. 2, a first inverter 32 is configured by a P-type MOST (PMOST) 40 and an N-type MOST (NMOST) 42 having each drain connected to an output signal node Q42, each gate electrode to an input signal node I42, a source of the PMOST 40 to a power supply line VDDL at a node VD42, and a source of the NMOST 42 to a power feedback line VSSL at a node VS42. Similarly, a second inverter 34 is configured by a PMOST 44 and an NMOST 46 having each drain connected to an output signal node Q44, each gate electrode to an input signal node I44, a source of the PMOST 44 to a power supply line VDDL at a node VD44, and a source of the NMOST 46 to a power feedback line VSSL at a node VS44. Moreover, the output signal node Q42 of the first inverter 32 is connected to the input signal node I44 of the second inverter 34, the output signal node Q44 of the second inverter 34 is connected to a drain (or a source) of a PMOST 50 serving as a feedback control transistor, and the source (or the drain) of the PMOST 50 is connected to the input signal node I42 of the first inverter 32, so that the positive feedback circuit (or the latch circuit) is configured when the PMOST 50 is in the conducted state. In addition, a gate of the PMOST 50 is connected to a word line CWL for supplying a feedback circuit control signal at a node P10, the input signal node I42 of the first inverter 32 is connected to a source (or a drain) of an NMOST 52 serving as a write control transistor, the drain (or the source) of the NMOST 52 is connected to a single bit line BL at a node D8, and a gate electrode thereof is connected to a write control signal line WWL for supplying a write control signal at a node P8. Moreover, the output signal node Q44 of the second inverter 34 is connected to a source (or a drain) of an NMOST 54, the drain (or the source) of the NMOST 54 is connected to the above-mentioned bit line BL at a node D9, and a gate electrode of the NMOST 54 is connected to a read control signal line RWL for supplying a read control signal at a node P9. A control circuit 60 controls appropriately the potentials of a decoder circuit for selecting the cell, the WWL line, the CWL line, or the RWL line to generate the control signals thereof.
Hereinafter, schematic operation will be described in simulations, in which the high level of the logic signal in the SRAM cell represents a potential VDD of the power supply line VDDL while the low level thereof represents a potential (ground, GND, 0 V) of the power feedback line VSSL.
FIG. 3 shows a circuit diagram of the conventional SRAM cell used in the simulations, in which a sense circuit is omitted for simplicity of description. The value of VDD is set to 0.7 V.
Although a storage device using the SRAM cells performing the write and read operations through a single bit line, as shown in FIG. 2, requires a measure against the malfunction due to noise voltage induced in the bit line, the so-called open bit line architecture can be employed as the measure, as with 1-capacitor DRAM cells. In FIG. 3, an inverter 86 (partial circuit surrounded by the dotted line) is configured by a PMOST 70 and an NMOST 72, and an inverter 88 (partial circuit surrounded by the dotted line) is configured by a PMOST 74 and an NMOST 76, where an output signal node of the inverter 86 and an input signal node of the inverter 88 are connected with each other. This node is referred to as Vcellhold. An input signal node of the inverter 86 and an output signal node of the inverter 88 are referred to as Vcellwrite and Vcellread, respectively, which are connected through an NMOST 84 serving as a feedback control transistor. The conducted/non-conducted state of the NMOST 84 is determined by a control signal Vfbcont applied to a gate thereof. The nodes Vcellread and Vcellwrite are connected to a single bit line BL through an NMOST 80 as the read control transistor and an NMOST 82 as the write control transistor, respectively. The conducted/non-conducted state of the NMOSTs 80 and 82 is determined by control signals Vwrl and Vwwl, respectively, applied to each gate electrode terminal. The bit line BL is connected with a load capacitor Cbit, assuming that a number of cells of other rows in the storage device array are connected therewith, and the potential thereof is controlled by a bit line potential control signal source Vbitsource through an NMOST 90. A gate electrode terminal of the NMOST 90 is applied with a control signal Vbitscont, so that the bit line BL can be set to the high impedance state (where the discharging/charging of charges is highly limited) by switching the NMOST 90 to the non-conducted state. Note that the node symbols also represent symbols of a signal waveform of the node.
In the simulations, conventional double insulated gate field effect transistors are used, where two gates of each one are connected commonly for three-terminal operation, as shown in a schematic diagram of FIG. 4. In FIG. 4, reference numeral 91 denotes a substrate, 92 denotes an insulator, 93 denotes a source region, 94 denotes a drain region, 95 denotes a channel region, 96-1 denotes a first gate oxide, 96-2 denotes a second gate oxide, 97 denotes a first gate, 98 denotes a second gate, and 99 denotes an insulator.
First, FIGS. 5 and 6 show simulation results of the write operation of the conventional SRAM cell in FIG. 2. FIG. 5 shows the control signal waveform of the write operation, and FIG. 6 shows the signal waveform of each node of the SRAM cell at that time.
Table 1 shows sample values of the control signal waveform of the write operation in FIG. 5. In FIG. 5, the horizontal axis represents Time (s: seconds) and the vertical axis represents Signal Swing (V).
The symbol Δ represents characteristics of Vfbcont (a signal of the feedback control signal line CWL; i.e. the feedback control signal); and
the symbol • represents characteristics of Vwwl (a signal of the write control signal line WWL; i.e. the write control signal).
The characteristics shown in FIG. 5 prove that Vfbcont and Vwwl exhibit consistent values alternately in the temporal basis.
Table 2 shows sample values of the signal waveform of each node of the SRAM cell in the write operation. In FIG. 6, the horizontal axis represents Time (s: seconds) and the vertical axis represents Signal Swing (V).
The symbol − represents characteristics of Vcellhold (hold voltage of the cell; i.e. the output node voltage of the first inverter);
the symbol + represents characteristics of Vcellwrite (write voltage of the cell; i.e. the input node voltage of the first inverter);
the solid line represents characteristics of Vcellread (readout voltage of the cell; i.e. the output node voltage of the second inverter); and
the symbol * represents characteristics of Vbitline (bit line voltage).
TABLE 1Time (s)Vfbcont (V)Vwwl (V)1.10E−101.401.20E−101.401.40E−10001.60E−10001.80E−1001.42.80E−1001.43.00E−10003.20E−10003.40E−101.405.60E−101.405.80E−1001.47.40E−101.408.00E−101.40
TABLE 2VcellholdTime (s)(V)Vcellwrite (V)Vcellread (V)Vbitline (V)1.10E−100.71.13E−069.35E−070.6906041.20E−100.71.13E−069.31E−070.6938581.45E−100.700197−0.128133−0.0001076750.6976461.61E−100.702212−0.1188440.0007231420.6987651.72E−100.7518380.3584847.86E−050.6966611.79E−100.1542560.6624520.002423040.695712.80E−102.13E−060.6999070.6999990.6999133.06E−10−7.73E−050.5619460.7000680.6987133.41E−100.000360770.7548760.7346510.6996613.63E−10−8.64E−050.7003550.7002360.6998573.76E−102.34E−060.6999910.6999940.6999124.20E−101.61E−070.70.70.6999855.60E−100.000194710.5273940.6999990.0001197815.92E−100.6992630.004489640.0001580910.004112287.07E−100.699969−0.08594181.10E−05−0.002047787.76E−100.7−8.42E−07−5.46E−07−2.10E−057.94E−100.7−5.22E−07−3.13E−07−6.13E−06
The swing of the control signal is set to be higher than the VDD, or 1.4 V as an example. This serves for prevention of the threshold voltage fall-off of a signal level when transferring the signals of the respective controlling NMOSTs 80, 82 and 84. The NMOST 90 to control the potential of the bit line BL is in the conducted state. That is, the control signal Vbitscont is held at 1.4 V, the potential Vbitline of the bit line BL is dependent on the potential of the control power source Vbitsource, and the bit line BL is in the low impedance state (where the charging/discharging of charges is highly easily performed).
When the nodes Vcellwrite and Vcellread are at the low level (0 V) and thus the node Vcellhold is at the high level (0.7 V) (the state being considered that the memory contents are at the low level), the write operation is performed to invert the memory contents. In other words, Vbitline is charged to reach the high level (0.7 V) and then the feedback control signal Vfbcont is shifted from 1.4 V to 0.0 V, as shown in FIG. 5, to switch the NMOST 84 to the non-conducted state, so that the nodes Vcellwrite and Vcellread are disconnected from each other. Next, the write control signal Vwwl is shifted from 0.0 V to 1.4 V to switch the NMOST 82 to the conducted state, and the potential of Vbitline is transferred to the node Vcellwrite. In doing so, the potential of Vcellwrite is shifted from the low level to the high level, which in turn shifts the potential of Vcellhold to the low level and then shifts the potential of Vcellread to the high level. When these potentials are stabilized, the level of Vwwl is returned to 0.0 V to switch the NMOST 82 back to the non-conducted state, and the level of Vfbcont is returned to 1.4 V to switch the NMOST 84 back to the conducted state, so that the inverters 86 and 88 configure the latch circuit to establish a holding status of the memory contents. The holding status continues while Vfbcont is kept at 1.4 V. Such a state where the nodes Vcellwrite and Vcellread are at the high level (0.7 V) and thus the node Vcellhold is at the low level (0.0 V) is considered that the memory contents are at the high level.
Next, the memory contents at the high level are rewritten by the memory contents at the low level. First, the potential of Vbitline is shifted from the high level to the low level. Then, as with the write procedure described above, the feedback control signal Vfbcont is shifted from 1.4 V to 0.0 V to switch the NMOST 84 to the non-conducted state, so that the nodes Vcellwrite and Vcellread are disconnected from each other. Then, the write control signal Vwwl is shifted from 0.0 V to 1.4 V to switch the NMOST 82 to the conducted state, and the potential of Vbitline is transferred to the node Vcellwrite. In doing so, the potentials of the respective nodes Vcellwrite, Vcellhold, and Vcellread are inverted, as shown in FIG. 6, so that the memory contents at the low level are written.
As described above, the write operation and the memory holding operation are proved to be performed correctly. Next, the read operation will be described. Note that the NMOST 82 is in the non-conducted state during the read operation. In other words, the write control signal Vwwl is kept at 0.0 V.
FIG. 7 shows the signal waveform of each node when reading the memory contents held at the low level from the conventional SRAM cell in FIG. 2. In FIG. 7, the horizontal axis represents Time (s: seconds) and the vertical axis represents Signal Swing (V).
The symbol ⋄ represents characteristics of Vcellhold (hold voltage of the cell);
the symbol □ represents characteristics of Vcellwrite (write voltage of the cell);
the symbol Δ represents characteristics of Vcellread (read voltage of the cell);
the symbol x represents characteristics of Vfbcont (a signal of the feedback control signal line CWL; i.e. the feedback control signal);
the symbol * represents characteristics of Vbitline (bit line voltage);
the symbol + represents characteristics of Vwrl (a signal of the read control signal line WRL; i.e. the read control signal);
the solid line with the symbol − represents characteristics of Vbitsource (voltage of the pulsed power supply for applying the potential of the bit line); and
the dashed line with the symbol − represents characteristics of Vbitscont (gate voltage to be applied to the NMOST for controlling the connection status between the pulsed power supply for applying the potential of the bit line and the bit line).
Table 3 shows sample values of the signal waveform of each node.
TABLE 3VcellholdVcellwriteVfbcontVwrlVbitsourceVbitscontTime (s)(V)(V)Vcellread (V)(V)Vbitline (V)(V)(V)(V)3.00E−100.73.45E−089.15E−081.4−3.86E−06001.43.40E−100.72.52E−072.50E−071.4−2.78E−08001.43.47E−100.76.99E−076.16E−071.40.023646800.113841.44.60E−100.71.01E−068.40E−071.40.34968200.351.44.80E−100.79.94E−078.27E−071.40.33646100.3505.00E−100.71.01E−068.36E−071.40.33646100.3505.20E−100.699128−0.129384−0.009153800.33645900.3507.00E−100.70002−0.121109−2.05E−0500.19921200.3507.20E−100.7025630.08580830.06701151.40.19921200.3507.93E−100.6999991.03E−068.48E−071.40.19921100.350
First, assuming that the open bit line architecture is applied for sensing, the bit line BL is charged to reach VDD/2. After the potential thereof is stabilized, the control signal Vbitscont to control the potential of the bit line BL is shifted from 1.4 V to 0.0 V to switch the NMOST 90 to the non-conducted state, so as to set the bit line BL to the high impedance state. Then, the feedback control signal Vfbcont is shifted from 1.4 V to 0.0 V, as shown in FIG. 7, to switch the NMOST 84 to the non-conducted state, so that the nodes Vcellwrite and Vcellread are disconnected from each other. Next, the read control signal Vwrl is shifted from 0.0 V to 1.4 V to switch the NMOST 80 to the conducted state, so that the bit line BL and the node Vcellread are connected to each other. Since the NMOST 76 of the inverter 88 is in the conducted state, the node Vcellread is in the low impedance state. Thereby, the charges charged on the bit line BL are discharged through the NMOSTs 80 and 76, as shown in FIG. 7, and then the potential Vbitline thereof decreases from VDD/2. From the decreased potential, a sense amplifier can detect that the memory contents are at the low level. Here, the potential of the node Vcellread is 0.0 V initially and increases immediately after the read operation is initiated. Although the extent of increase is dependent on the ratio of impedances of the NMOSTs 80 and 76, it is clearly lower than the potential VDD/2 of the bit line BL, which is set at the initiation of the read operation. However, if the potential of the bit line BL increases further due to the noises not considered in the simulations so that the potential of the node Vcellread exceeds a logic threshold (approximately VDD/2) of the inverter 86, the memory contents would not be inverted because the nodes Vcellwrite and Vcellread are disconnected from each other. After the end of the read operation, the control signal is returned to 0.0 V and the NMOST 80 is switched back to the non-conducted state. Moreover, the feedback control signal Vfbcont is returned to 1.4 V, the NMOST 84 is switched back to the conducted state, and thus the SRAM cell returned to the memory holding status at the low level, so that the memory contents are not inverted.
FIG. 8 shows the signal waveform of each node when reading the memory contents held at the high level from the conventional SRAM cell in FIG. 2. In FIG. 8, the horizontal axis represents Time (s: seconds) and the vertical axis represents Signal Swing (V).
The symbol ⋄ represents characteristics of Vcellhold (hold voltage of the cell);
the symbol □ drawn in front of the line represents characteristics of Vcellwrite (write voltage of the cell);
the symbol Δ represents characteristics of Vcellread (read voltage of the cell);
the dashed line with the symbol x represents characteristics of Vfbcont (a signal of the feedback control signal line CWL; i.e. the feedback control signal);
the symbol * represents characteristics of Vbitline (bit line voltage);
the dashed line with the symbol + represents characteristics of Vwrl (a signal of the read control signal line WRL; i.e. the read control signal);
the symbol □ drawn behind the line represents characteristics of Vbitsource (voltage of the pulsed power supply for applying the potential of the bit line); and
the dashed line with the symbol − represents characteristics of Vbitscont (gate voltage to be applied to the NMOST for controlling the connection status between the pulsed power supply for applying the potential of the bit line and the bit line).
Table 4 shows sample values of the signal waveform of each node.
TABLE 4VcellwriteVfbcontVbitlineVwrlVbitsVbitsTime (s)Vcellhold (V)(V)Vcellread (V)(V)(V)(V)(V)cont(3.00E−10−0.00277140.5614520.70011200.69839300.71.43.23E−100.004185790.5768310.709170.1822490.69932400.71.43.40E−100.01004830.7642210.7484151.40.69965200.71.44.40E−102.17E−070.70.71.40.69999400.71.45.10E−102.46E−070.70.71.40.36389700.351.45.30E−102.46E−070.70.71.40.34628100.3505.60E−102.44E−070.70.71.40.3462800.3505.80E−10−0.00303620.5261270.692741.22E−150.3462800.3506.00E−10−0.00606970.5252390.47996200.3590231.40.3507.00E−100.000608020.5279650.53123100.4512671.40.3507.20E−100.000589720.527960.69249500.45293100.3507.56E−100.000192170.5277970.69999900.4529300.3507.80E−100.01150860.7575830.7445331.40.4529300.3508.00E−10−0.00016310.7006690.7004451.40.4529300.350
After the potential of the bit line BL is stabilized at VDD/2, the control signal Vbitscont to control the potential of the bit line BL is shifted from 1.4 V to 0.0 V to switch the NMOST 90 to the non-conducted state, so as to set the bit line BL to the high impedance state. Then, the feedback control signal Vfbcont is shifted from 1.4 V to 0.0 V, as shown in FIG. 8, to switch the NMOST 84 to the non-conducted state, so that the nodes Vcellwrite and Vcellread are disconnected from each other. Next, the read control signal Vwrl is shifted from 0.0 V to 1.4 V to switch the NMOST 80 to the conducted state, so that the bit line BL and the node Vcellread are connected to each other. Since the PMOST 74 of the inverter 88 is in the conducted state and thus the node Vcellread is connected to the power source VDD, the bit line BL is charged further through the NMOST 80 and PMOST 74, as shown in FIG. 8, and then the potential Vbitline thereof increases from VDD/2. From the increased potential, the sense amplifier can detect that the memory contents are at the high level. Here, the potential of the node Vcellread is 0.7 V initially and decreases immediately after the read operation is initiated. The extent of decrease is dependent on the ratio of impedances of the NMOST 80 and the PMOST 74. However, if the potential decreases below the logic threshold of the inverter 86 due to the noises or the like, which is the situation that is not considered in the simulations, the memory contents would not be inverted because the nodes Vcellwrite and Vcellread are disconnected from each other. After the end of the read operation, the control signal is returned to 0.0 V and the NMOST 80 is switched back to the non-conducted state. Moreover, the feedback control signal Vfbcont is returned to 1.4 V, the NMOST 84 is switched back to the conducted state, and thus the SRAM cell returned to the memory holding status at the high level, so that it can be found that the memory contents are not inverted as well.
The read operation is also proved to be performed correctly as described above, while it is found that there is the possibility for improvements. The disadvantage is that the potential of the node Vcellwrite in FIGS. 7 and 8 decreases when the feedback control signal Vfbcont is shifted from 1.4 V to 0.0 V. The potential is shifted below zero temporarily in FIG. 7, and below the high-level potential VDD in FIG. 8. This is because the NMOST 84 is switched to the non-conducted state and thus the node Vcellwrite is set to the high impedance state, that is the state where there is no passage sufficient for the charges to be discharged/charged to hold the potential, resulting in the redistribution of the accumulated charges in order to meet the condition that, when one potential of the stray capacitance loaded on the node Vcellwrite is shifted, the stray capacitance accumulates the charges as well corresponding to the change in the potential. In other words, the amount of the charges accumulated in the stray capacitance between the gate of the NMOST 84 and the node Vcellwrite changes in response to the change in the potential of the gate terminal of the NMOST 84. Although the problems did not occur in the simulations, with the additional noises, the negative potential as with the case in FIG. 7 may cause the increase in leak current induced by the gate (so-called GIDL) or the failure of the gate oxide, and the potential decrease from the high level as with the case in FIG. 8 may cause the inversion of the memory contents. Therefore, it is desirable to realize the SRAM cell without these causes. It is also desirable to reduce the number of the control signal lines from three of them for a pair of read and write ports as can be seen in the SRAM cell of FIG. 2.
In FIG. 2, there is required the read control signal line RWL and the write control signal line WWL in the row direction of the SRAM storage device as well as the feedback control signal line CWL in the different row direction in order to control the feedback control transistor to be switched to the non-conducted state when the write and read operations are performed. However, if it is sufficient to reserve a noise margin only for the write operation, one of the control signal lines can be eliminated by replacing the feedback control transistor with a PMOST and connecting a gate electrode terminal thereof to the write control signal line WWL. This is because the feedback control transistor may be in the conducted state when the write control NMOST is in the non-conducted state, or vice versa. However, the feedback control PMOST is switched to the conducted state when the read operation is performed, so that the noise margin is lowered in the read operation. In other words, in the read operation, the potential change in the output signal node Q44 (Vcellread in FIG. 3) of the second inverter 34 directly causes the potential change in the input signal node I42 (Vcellwrite in FIG. 3) of the first inverter 32, leading to the increase in the risk to cause the inversion of the output of the first inverter 32 (the inverter 86 in FIG. 3), i.e. the inversion of the memory contents, due to the noises and the like. In order to avoid this to occur, Patent Document 2 discloses an SRAM cell 100 shown in FIG. 9 additionally including a read buffer configured by a read control transistor and a buffer transistor as well as a read-only bit line.
In the SRAM cell 100 in FIG. 9, an inverter 102 is configured by a PMOST 110 and an NMOST 112 having each drain connected to form an output signal node Q102, each gate to form an input signal node I102, a source of the PMOST 110 to a power supply line VDDL, and a source of the NMOST 112 to a power feedback line VSSL. Similarly, an inverter 104 is configured by a PMOST 114 and an NMOST 116 having each drain connected to form an output signal node Q104, each gate to form an input signal node I104, a source of the PMOST 114 to a power supply line VDDL, and a source of the NMOST 116 to a power feedback line VSSL. Moreover, the output signal node Q102 of the inverter 102 is connected to the input signal node I104 of the inverter 104, the output signal node Q104 of the inverter 104 is connected to a drain (or a source) of a PMOST 120 serving as a feedback control transistor, and the source (or the drain) of the PMOST 120 is connected to the input signal node I102 of the inverter 102, so that the positive feedback circuit (or the latch circuit) is configured when the PMOST 120 is in the conducted state. In addition, a gate of the PMOST 120 is connected to a write control signal line WWL, the input signal node I102 of the inverter 102 is connected to a source (or a drain) of an NMOST 122 serving as a write control transistor, and the drain (or the source) of the NMOST 122 is connected to a write-only bit line W-BL. Moreover, the output signal node Q102 of the inverter 102 is connected to a gate of an NMOST 124 serving as a buffer transistor, a source of the NMOST 124 is connected to the power feedback line VSSL, a drain of the NMOST 124 is connected to a source (or a drain) of an NMOST 126 serving as a read control transistor, the drain (or the source) of the NMOST 126 is connected to a read-only bit line R-BL, and a gate of the NMOST 126 is connected to a read control signal line RWL. A control circuit 130 provides appropriate control signals to a decoder circuit for selecting the cell, the WWL, or the RWL.